The formation of a damascene interconnect in a groove formed in an insulating film requires that conductive material be deposited only within the insulator groove. Therefore, precise manufacturing steps are required to ensure that the interconnect is formed only within the groove and does not overflow onto the surface of the insulating film in which the insulator groove is formed.
Fabrication of damascene interconnects is currently accomplished using a physical vapor deposition (PVD) process for depositing tungsten followed by a chemical mechanical polishing (CMP) process as illustrated in prior art FIG. 1. In FIG. 1A, a groove 110 is formed in a silicon dioxide or other insulating layer 100 by photoresist patterning followed by reactive ion etching (RIE). A conductor 102 is then deposited using physical vapor deposition (PVD) as shown in FIG. 1B. This conductive layer 102 is then polished using CMP as shown in FIG. 1C. This CMP process causes a residue 103, e.g., SiO.sub.2 clusters, to be formed within the groove 110. When tungsten or other interconnect material is subsequently deposited in the groove using a PVD process, this residue inhibits the growth of selectively deposited tungsten from the bottom of the groove 110. Thus, the interconnect material grows more readily from the sidewalls of the groove than from the bottom of the groove, causing the tungsten or other interconnect material to overflow the groove 110. The resulting overfill (shown in FIG. 1D) must be removed using CMP. Because CMP is utilized to remove conductive layer 102, the residue may cause shorts between interconnects. The residue 103 between the tungsten or other interconnect material and the conductor 102 at the bottom of the groove may also cause opening problems.
Other known tungsten interconnect fabrication methods are described in U.S. Pat. Nos. 4,764,484 and 4,948,755; and E. K. Broadbent et al., "High-Density, High-Reliability Tungsten Interconnection by Filled Interconnect Groove Metalization," from IEEE Transactions on Electron Devices, vol. 35 (1988) at page 952. The '484 and '755 patents describe a fabrication process using a thin silicon layer at the bottom of the groove which is consumed during the selective CVD tungsten deposition. However, this fabrication method may result in shorts between interconnects, even when intrinsic silicon is used. Also, tungsten encroachment occurs in the lateral direction during the silicon consumption process, further increasing the short problem. The Broadbent article describes a fabrication process in which blanket CVD tungsten and RIE etchback are used instead of CMP in the formation of a damascene interconnect. However, the non-uniformity of the RIE etchback may create a step between the oxide and the tungsten surface such that the performance of the interconnect is compromised.
Accordingly, it is an object of the present invention to provide a residue-free surface at the bottom of the insulator groove in which a damascene interconnect is to be formed, thereby enabling growth of selectively deposited tungsten (or other material) on the bottom of the groove.
It is another object of the present invention to provide a method of fabricating a damascene interconnect using selective chemical vapor deposition of tungsten (or other interconnect material) instead of physical vapor deposition of the interconnect material such that the deposited tungsten or other interconnect material deposited grows more readily from the bottom of the insulator groove rather than from the sidewalls of the insulator groove, thereby reducing or eliminating the need for CMP and improving the performance of the interconnect.